1. Field of the Invention
This invention relates to sample and hold circuits, and more particularly to sample and hold circuits in which a bridge circuit interfaces between the input and output terminals so that the output voltage tracks that at the input.
2. Description of the Related Art
Sample and hold circuits are used to track an input analog signal, and then hold a sampled value of the signal when a sample command is applied. The circuit is typically cycled between track and hold modes, with successive samples normally taken at a rate at least equal to the Nyquist frequency.
A prior sample and hold circuit is illustrated in FIG. 1. It includes a diode bridge circuit 2, with an analog input signal Vin applied to one side of the bridge through an input buffer amplifier A1, and an output signal Vo taken from the opposite side of the bridge through an output resistor Rh. The circuit is configured so that Vo tracks Vin and charges an output holding capacitor Ch at the output terminal.
The alternation between track and hold modes is controlled by a differential pair of bipolar transistors Q1 and Q2, with a hold control signal Vh applied to the base of Q1 and a sample signal Vs applied to the base of Q2. The collectors of Q1 and Q2 (in the npn configuration illustrated) are respectively connected to a current input node N1 and a current output node N2 of the bridge 2, while their emitters are differentially connected to a bias current source I1 that draws a bias current Ib through the differential pair. A second current source I2 provides a current equal to Ib/2 to the bridge's input current node N1, while a third current source I3 provides an equal value of current Ib/2 to the bridge's output current node N2. I2 and I3 are connected to a positive voltage supply bus Vcc, while I1 is connected to a negative voltage bus Vee. A current diversion circuit, consisting of series-connected diodes D1 and D2, conducts current from N2 to N1 during a hold mode to bypass the bridge circuit. A bootstrap amplifier A2 is connected between the output terminal Vo and the connection between D1 and D2, forcing a replication of the output voltage at the D1/D2 interconnection.
During the track mode, Vs is applied to Q2 so that Q2 conducts and Q1 is inactive. The current from I2 thus divides between the input and output branches of the bridge circuit 2 and flows out of the bridge at node N2, where it combines with the current from I3. The combined Ib/2 currents from I2 and I3 then flow through Q2 to provide the Ib current drawn by I1. The activation of the bridge circuit causes the output voltage at Vo to track the input voltage Vin, with transient changes in the input voltage causing transient currents to flow into or out of the holding capacitor Ch to maintain the voltage tracking.
When Vs is replaced by a hold signal Vh applied to Q1, Q2 is cut off and current no longer flows through the diode bridge. The current from I2 instead flows into I1 through Q1, while the current from I3 flows into Q1 through the D1/D2 diversion circuit. Since current flows through D1 and D2 in the direction from N2 to N1, which is opposite to the direction of current flow through the diode bridge 2, the forward voltage drops across D1 and D2 reverse bias the bridge diodes; D1 and D2 can each be implemented by two or more series connected diodes to generate a sufficient voltage drop to reverse bias the bridge diodes.
The diode bridge D2 of FIG. 1 does not provide current gain or reverse isolation, so the buffer amplifier A1 is required to achieve wide bandwidth sampling. Significant amounts of bias current must be used to achieve low distortion operation, and the I3 current that bypasses the bridge during the track mode is simply wasted.
FIG. 2 shows a modification of FIG. 1, with elements common to both figures identified by the same reference numerals, in which the full bias current flows through the diode bridge during the track mode. Instead of the two current sources I2 and I3, each of which supply half the bias current, a single current source I4 is provided with a full bias current value. I4 is connected to both node N1 through the emitter-collector circuit of a pnp bipolar transistor Q3, and to node N2 through the emitter-collector circuit of a second pnp bipolar transistor Q4. An inverted value of the sample control signal Vs is delivered to the base of Q3 through an invertor INV1, while an inverted value of the hold control signal Vh is delivered to the base of Q4 through a second invertor INV2. In the track mode Q2 and Q3 are active, Q1 and Q4 are cut off, and the bias current flows through the diode bridge 2 so that the voltage at Vo tracks the input voltage Vin. During the hold mode Q1 and Q4 are active, Q2 and Q3 are cut off, and the bias current from I4 flows in succession through Q4, D1, D2 and Q1 into current source I1, bypassing the diode bridge so that the output terminal holds the value of the output voltage at the moment the hold mode was entered.
While the circuit of FIG. 2 has less power wastage than FIG. 1, the current available to charge or discharge the holding capacitor Ch is still limited to the diode standing current in the bridge 2, and the slew rate of the input signal that the circuit can handle is limited.